Performance Limits Due to Inter-Cluster Data Forwarding in Wire-Limited ILP Microprocessors

The growing speed gap between transistors and wire interconnects is forcing the development of distributed, or clustered, architectures. These designs partition the chip into small regions with fast intra-cluster communication. Longer latency is required to communicate between clusters. The hardware and/or software is responsible for scheduling instructions to clusters such that critical path communication occurs within a cluster. This paper explores fundamental interactions between semiconductor technology and clustered architectures. The relationship between key technology parameters (inter-cluster wire delay and transistor switching delay) and key architecture parameters (superscalar vs multithreaded instruction dispatch, and value prediction support) is investigated. The GENESYS modeling tool is used to predict inter-cluster latencies as VLSI technology advances. The study shows that performance limits of the conventional superscalar approach are substantially higher with zero-delay wires. As wire delay increases, performance of these designs degrade quickly. Threaded designs are more tolerant to wire delay. It is seen that the optimal thread size changes with advancing VLSI technology, suggesting a highly adaptive architecture. Value prediction is shown to be useful in all cases, but provides more benefit to the multi-threaded design.